The invention relates to an embedded system, more particularly to an embedded system with an instruction prefetching device and to a method for fetching instructions in embedded systems.
FIG. 1 illustrates a conventional embedded system 5 that comprises a system bus 54, a processor 51 coupled to the system bus 54, a memory controller 52 coupled to the system bus 54, a peripheral controller 53 coupled to the system bus 54, and a memory device 55 coupled to the memory controller 52. The peripheral controller 53 may be various controllers or drivers coupled to the system bus 54 and can be controlled by the processor 51. For example, in a cellular phone applications, the peripheral controller 53 may be a controller to control the LCD or a controller to control the keypad of a cellular phone. Rather than being coupled to the system bus 54 directly, in this example the memory device 55 is coupled to the memory controller 52 for being controlled and being accessed by the memory controller 52.
When the processor 51 wants to fetch instruction from the memory device 55, the processor 51 will issue an access request having a target address directed to the memory controller 52. The memory controller 52 then fetches an instruction from the memory device 55 according to the access request received from the processor 51, and provides the instruction to the system bus 54 for receipt by the processor 51. When the processor 51 is accessing the memory device 55, the system bus 54 will be occupied since it has to relay the access requests issued by the processor 51 to the memory controller 52 and relay the fetched instructions from the memory controller 52 to the processor 51.
Aside from accessing the memory device 55, the processor 51 can also access the peripheral controller 53. When the processor 51 wants to access the peripheral controller 53, the processor 51 will issue an access request having a target address directed to the peripheral controller 53. Apparently, when the processor 51 is accessing the peripheral controller 53, the system bus 54 will be occupied since it has to relay the access requests and information corresponding to the access requests between the processor 51 and the peripheral controller 53.
Besides, the peripheral controller 53 and another peripheral controller (not shown) can also exchange information through the system bus 54, causing the system bus 54 to be occupied by the two peripheral controllers.
Although the conventional embedded system has a lower system performance, it works well in various applications. However, as the embedded system 5 becomes more complex, the embedded system 5 is required to run at higher speeds to achieve better performance. More particularly, access latency occurs during fetching of an instruction from the memory device 55 after the processor 51 sent out an access request (i.e., fetching cycle), so the performance of the processor 51 is degraded. For the conventional embedded system, the fetching cycle occupies approximately 30%˜50% of the instruction cycle of the processor 51, so access latency is a problem which cannot be ignored.
Two methods are proposed in the related art in order to overcome the above problem.
1. An additional cache memory (L2 cache) is incorporated to increase the memory bandwidth, so as to enhance the performance of the embedded system. However, the cache memory (such as an SRAM) has a higher cost and a relatively small memory capacity.
2. When the processor 51 executes an instruction, fetching of a next instruction is executed at the same time. This kind of solution is referred to as instruction prefetching. However, the occupation period of the system bus 54 becomes longer when the next instruction is among a series of consecutive instructions or has too many branch instructions. Data access to or from the peripheral controller 53 must wait until fetching of the next instruction has been completed by the processor 51. Similarly, when two peripheral controllers 53 are exchanging information, the processor 51 also have to wait a period for the system bus 54 to be freed.
In other words, as long as the system bus 54 is occupied, other information access processes relying on the system bus 54 have to wait until the system bus 54 is freed. FIG. 2 is a timing chart to illustrate an operating example of the conventional embedded system 5. The system bus 54 is occupied by the instruction fetch phase and the data access phase in turns. In the instruction fetch phase, the processor 51 communicates with the memory controller 52 and instructions or data stored in the memory device 55 are fetched; whereas in the data access phase, the processor 51 communicates with the peripheral controller 53 and requests the peripheral controller 53 to perform certain actions. Alternately, in the data access phase, the peripheral controller 53 is communicating with another peripheral controller (not shown) through the system bus 54. As such, when the system bus 54 is in the data access phase while one peripheral controller 53 is communicating with another peripheral controller 53, the processor 51 have to remain idle for a period of time (about two bus cycles) before it is allowed to communicate with the memory controller 52.
In addition, when the system bus 54 is occupied since the processor 51 is accessing the peripheral controller 53 or two peripheral controllers 53 are exchanging information, even if the memory controller 52 is idle the processor 51 still have to wait for a period of time (about two bus cycles) before it is allowed to communicate with the memory controller 52. Therefore, it is preferred that the memory controller 52 prefetches instructions from the memory device 55 while the system bus 54 is occupied by the processor 51 and the peripheral controller 53 or by two peripheral controllers. After the system bus 54 is freed, the memory controller 52 can send the prefetched instructions, which conform to the requirements of the processor 51, to the processor 51 in response to the request issued by the processor 51. The performance of the whole embedded system is therefore increased. An objective of the present invention is to propose a solution to this kind of problem.